The invention is directed to a method for producing an insulation, particularly a well insulation, between two regions of different conductivity in a semiconductor component.
The goal of many developments in electronics is to continuously reduce the costs to be expended for the realization of a specific electronic function and, thus, to continuously increase the productivity. This enhancement of the productivity was and is particularly achieved by an increased integration of the electronic functions. The increase in the integration of the electronic functions is in turn mainly achieved by a progressive structural miniaturization of the individual components.
Logic circuits, which are usually manufactured with a CMOS process, are usually composed of n-channel or, respectively, p-channel MOS transistors. Thus, the corresponding substrate regions are formed by p-wells or, respectively, n-wells. The demand that the expanse of the circuits be reduced farther and farther is opposed, among other things, by the technology-dependent minimum distance between neighboring n-regions and p-regions. This minimum distance is one of the most important design rules for CMOS circuits. In particular, the minimum distance contributes to avoiding a latch-up effect that is produced by the formation of parasitic thyristor structures between neighboring n-channel and p-channel transistors.
A number of measures are known for further reducing the minimum distance between neighboring n-regions and p-regions without thereby simultaneously increasing the risk of the latch-up effect. In the case of an n-well, first, the p-substrate can be provided wiht a negative bias or, respectively, a p+-substrate wiht a p-epitaxial layer can be employed. An additional measure is by employing optimally many well and substrate contacts and thereby keeping the potential in the well and in the substrate constant and, therefore, avoiding voltage drop-offs that can trigger a latch-up.
The aforementioned measures, however, respectively require additional process steps, as a result whereof the overall process becomes more involved and, thus, expensive. Moreover, the minimum distance between neighboring n-regions and p-regions can thereby be diminished to only an extremely limited extent.
Over and above this, an increasing need for application-specific integrated semiconductor products will arise in the future that, in addition to comprising the logic units that are required for the respective applied purpose, also comprise memory units with memory capacities that are individually matched to the respective requirements. xe2x80x9cEmbedded solutionsxe2x80x9d or xe2x80x9cembedded DRAM-productsxe2x80x9d are mentioned in this context. It has been found that a clear increase in the system performance is achieved by the integration of RAM structures on the application-specific semiconductor product. Given such an arrangement, thus, memory accesses can often be implemented within one system clock.
An example is integrated semiconductor products for speech analysis and speech recognition and these products store the signals that represent the spoken language in an integrated memory for a certain time so that the logic units are in the position to analyze the signals. Additional examples are controller modules or DSP structures that comprise DRAM memory cells in order to carry out their function as efficiently as possible. Entire systems (xe2x80x9csystems on siliconxe2x80x9d) that are integrated in a single module are then often formed in this way.
Whereas pure logic circuits are constructed essentially only of transistors, a DRAM memory cell comprises both a transistor as well as a capacitor that stores the charge needed for the presentation of the information. The capacitor of the memory cell has electrodes of doped silicon or, respectively, polysilicon and a dielectric layer of silicon dioxide and/or silicon nitride arranged between the electrodes.
In order to be able to reproducibly read out the charge stored in a capacitor, a capacitance of approximately 30 fF is required for the capacitor. The simultaneous demand to constantly diminish the lateral expanse of the capacitor in order to achieve an increase of the storage density led to the use of either trench capacitors, wherein the capacitor extends vertically into the substrate, or what are referred to as stack capacitors, wherein the capacitor is arranged above the transistor in the memory cell.
Of course, the technological outlay in the manufacture of the module also rises due to the integration of extensive logic circuits and memory cells in a single module. An additional compulsion to reduce the area occurs at the same time. Since a significant part of the area of a module must be employed for the insulation, there is great interest in an optimally space-saving insulation. Over and above this, however, the insulation should be manufacturable without great additional outlay in order to keep the costs of the overall process low.
The invention is therefore based on the object of disclosing a method for producing an insulation that satisfies said demands. Another object of the present invention is to make a corresponding semiconductor component available.
Inventively, a method for the simultaneous production of storage capacitors and at least one well insulation in a semiconductor substrate is offered. The inventive method comprises the steps:
a) providing a semiconductor substrate having at least one first region for the acceptance of the storage capacitors and at least one second region for the acceptance of the insulation;
b) using an etching technique to generate a plurality of trenches in the first region and at least one trench in the second region, whereby the trenches in the first region and the trench or, respectively, trenches in the second region have a depth of more than 2 xcexcm;
c) using a doping technique to create or generate a respectively first electrode on the trench walls at least in the first region;
d) using a film technique to create a respective dielectric in the trenches at least in the first region;
e) using a film technique to form or generate a respectively second electrode in the trenches at least in the first region, so that storage capacitors are formed in the first region; and
f) implementing at least one well implantation, so that at least one well region that is laterally limited by the trenches is generated in the second region.
The inventive method has the advantage that the process steps are applied both in the first as well as in the second region of the substrate, so that the structures in the different regions of the substrate that are achieved by the respectively same process steps serve different functions. A plurality of storage capacitors are generated in this way in the first region, and the essentially same structure is employed as a well insulation in the second region. Since storage capacitors need very deep trenches ( greater than 2 xcexcm), a very good insulation can be produced in this way without additional process outlay. Accordingly, the distances between individual components or between wells having different conductivity types can be clearly reduced without increasing the risk of what is referred to as a xe2x80x9clatch-upxe2x80x9d. Thus, for example, the minimum distance between an n-channel transistor and a p-channel transistor can be reduced by about 30%.
According to a preferred embodiment, the trench in the second region is formed as a closed curve. For example, an n-well can be insulated from a p-substrate in this way.
In step c), dopant diffusion from a doping layer is preferably employed as the doping technique. Particularly given deep trenches, a doping of the trench walls can be most easily implemented in this way. It is thereby preferred when arsenic glass, which can be deposited with an arsenic-TEOS method, is employed as the doping layer.
It is also preferred when an NO-layer or ONO-layer is employed as the dielectric and a polysilicon which is doped in situ is employed as an electrode.
According to another preferred embodiment, the first electrodes are formed only in the first region. By fashioning a first electrode in the second region, a leakage path can be formed along the trench surface, which path impedes good insulation. It is therefore advantageous when the first electrodes are formed only in the first region. In this way, the distances between individual components or between wells having different conductivity types can be further reduced.
When dopant diffusion from a doping layer is employed as the doping technique, then it is preferred that the doping layer in the second region is removed before the dopant diffusion from the trench. It is thereby preferred that the dopant layer is removed from the trench with an etching. The first region is preferably covered with a resist mask during this etching, so that the doping layer remains in the trenches in the first region. An additional mask that covers the memory cell field is required for this purpose during the execution of the process.
It is also preferred that the second electrodes are formed only in the first region. When polysilicon which is doped in situ is employed as the second electrode, then it is preferred that the polysilicon is in turn removed from the trench in the second region after the deposition. It is thereby preferred that the polysilicon is removed from the trench with an etching. The first region is preferably covered with a resist mask during this etching, so that the polysilicon remains in the trenches in the first region. An additional mask that covers the memory cell field is again required for this purpose during the process execution. The same mask used for the removal of the doping layer can be employed for the removal of the polysilicon.
It is also preferred that insulating material is deposited in the trench in the second region instead of the second electrode. Silicon oxide or undoped polysilicon can be advantageously employed for this purpose.
By combining these measures, a well insulation can be achieved wherein the spacing of the active components, for example transistors or diodes, across the well boundary is only limited by the process tolerances. Overall, the spacings of the active components across the well boundaries can be reduced by about 50% compared to a traditional insulation (xe2x80x9clocosxe2x80x9d or xe2x80x9cshallow trench insulationxe2x80x9d). The chip area that is saved is correspondingly large, and this can now be utilized for other jobs.